Conventional PIN diodes include an n+ type layer that is a cathode layer, an n− type layer formed on the n+ type layer, a p− layer that is partially formed in a surface layer of the n− type layer and is an anode layer, and p type layers formed in the surface layer of then n− type layer to be spaced apart from each other and formed to enclose the p− layer in a plan view.
With such a structure, the p− layer and the n+ type layer can increase a modulation level and achieve low ON-resistance (low Vf). To adjust the modulation level, a structure for maintaining almost constant, in a depth direction, an impurity concentration of the p− layer that is an anode layer and an impurity concentration of the n+ type layer that is a cathode layer is disclosed (see, for example, Patent Document 1).